Accessing makefile from multiple makefiles at the same time

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Accessing makefile from multiple makefiles at the same time

Tanya Smirnova
Hello,



I have a question about running two makefiles that both include the same
third makefile. The third, common, makefile generates a file – “outfile.h”.
As an input it takes a path to the output directory, and input files from
which to produce the generated output. Those two inputs are provided by the
first two makefiles. The generated “outfile.h” is used in the source of the
project1 and project2. I ran the “make” with “–j6” option.





Project1

Project2



                    makeFile1



in “makeFile1”:



       OUTPUT_DIR = path1

       INPUT_FILES = \

              In_file1\

              In_file2



include common_makefile





                makeFile2



in “makeFile2”:



       OUTPUT_DIR = path2

       INPUT_FILES = \

              In_file3\

              In_file4



include common_makefile






common_makefile



in “common_makefile”:



  ifndef _COMMON_MAKEFILE_

       _COMMON_MAKEFILE_ = 1



       OUT_FILE := $(OUTPUT_DIR)\outfile.h

       OUT_FILE : INPUT_FILES

               COMMAND



  endif



In Project1:



Use “outfile.h”

Project2:



“Use outfile.h”





When I ran a script that calls those two makefiles close to each other, the
files are not generated. Though, I see the OUTPUT_DIR is created for
project2.

If I comment the “  ifndef _COMMON_MAKEFILE_ … endif” block in the
“common_makefile”, and ran the script again, then I get the generated
“outfile.h” in the OUTPUT_DIR for project2,

but the content of it tells me that it’s a file for project1. So, it seems,
some race condition is happening when accessing the common_makefile at the
same time. Is there a way to run the “common_makefile” sequentially, first,
for project1, and then, for project2? Thank you.





Tanya.
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Re: Accessing makefile from multiple makefiles at the same time

Tim Murphy-4
Hi,

Rules are expanded just before they are executed so they get whatever
variables are set at that time (which is after all the parsing has
completed).

It depends what command you are using (e..g if it only uses the automatic
variables then you may get away with this) but if it references
$(OUTPUT_DIR) then the rule will see whatever the final version of
OUTPUT_DIR was.

e.g.:
.PHONY: all a b
all: a b

X:=1
a:
    echo $(X)

X:=2
b:
    echo $(X)

This will print
echo 2
2
echo 2
2


I usually got around this by using eval to ensure that the entire
target+rule was fully expanded at the time of parsing but you can also use
target specific variables.  e.g.
OUT_FILE: OUTPUT_DIR=project1

Regards,

Tim

On Thu, 14 Mar 2019 at 13:14, Tanya Smirnova <[hidden email]> wrote:

> Hello,
>
>
>
> I have a question about running two makefiles that both include the same
> third makefile. The third, common, makefile generates a file – “outfile.h”.
> As an input it takes a path to the output directory, and input files from
> which to produce the generated output. Those two inputs are provided by the
> first two makefiles. The generated “outfile.h” is used in the source of the
> project1 and project2. I ran the “make” with “–j6” option.
>
>
>
>
>
> Project1
>
> Project2
>
>
>
>                     makeFile1
>
>
>
> in “makeFile1”:
>
>
>
>        OUTPUT_DIR = path1
>
>        INPUT_FILES = \
>
>               In_file1\
>
>               In_file2
>
>
>
> include common_makefile
>
>
>
>
>
>                 makeFile2
>
>
>
> in “makeFile2”:
>
>
>
>        OUTPUT_DIR = path2
>
>        INPUT_FILES = \
>
>               In_file3\
>
>               In_file4
>
>
>
> include common_makefile
>
>
>
>
>
>
> common_makefile
>
>
>
> in “common_makefile”:
>
>
>
>   ifndef _COMMON_MAKEFILE_
>
>        _COMMON_MAKEFILE_ = 1
>
>
>
>        OUT_FILE := $(OUTPUT_DIR)\outfile.h
>
>        OUT_FILE : INPUT_FILES
>
>                COMMAND
>
>
>
>   endif
>
>
>
> In Project1:
>
>
>
> Use “outfile.h”
>
> Project2:
>
>
>
> “Use outfile.h”
>
>
>
>
>
> When I ran a script that calls those two makefiles close to each other, the
> files are not generated. Though, I see the OUTPUT_DIR is created for
> project2.
>
> If I comment the “  ifndef _COMMON_MAKEFILE_ … endif” block in the
> “common_makefile”, and ran the script again, then I get the generated
> “outfile.h” in the OUTPUT_DIR for project2,
>
> but the content of it tells me that it’s a file for project1. So, it seems,
> some race condition is happening when accessing the common_makefile at the
> same time. Is there a way to run the “common_makefile” sequentially, first,
> for project1, and then, for project2? Thank you.
>
>
>
>
>
> Tanya.
> _______________________________________________
> Help-make mailing list
> [hidden email]
> https://lists.gnu.org/mailman/listinfo/help-make
>
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Re: Accessing makefile from multiple makefiles at the same time

Tim Murphy-4
oops:

$(OUT_FILE): OUTPUT_DIR=project1

On Fri, 15 Mar 2019 at 06:05, Tim Murphy <[hidden email]> wrote:

> Hi,
>
> Rules are expanded just before they are executed so they get whatever
> variables are set at that time (which is after all the parsing has
> completed).
>
> It depends what command you are using (e..g if it only uses the automatic
> variables then you may get away with this) but if it references
> $(OUTPUT_DIR) then the rule will see whatever the final version of
> OUTPUT_DIR was.
>
> e.g.:
> .PHONY: all a b
> all: a b
>
> X:=1
> a:
>     echo $(X)
>
> X:=2
> b:
>     echo $(X)
>
> This will print
> echo 2
> 2
> echo 2
> 2
>
>
> I usually got around this by using eval to ensure that the entire
> target+rule was fully expanded at the time of parsing but you can also use
> target specific variables.  e.g.
> OUT_FILE: OUTPUT_DIR=project1
>
> Regards,
>
> Tim
>
> On Thu, 14 Mar 2019 at 13:14, Tanya Smirnova <[hidden email]> wrote:
>
>> Hello,
>>
>>
>>
>> I have a question about running two makefiles that both include the same
>> third makefile. The third, common, makefile generates a file –
>> “outfile.h”.
>> As an input it takes a path to the output directory, and input files from
>> which to produce the generated output. Those two inputs are provided by
>> the
>> first two makefiles. The generated “outfile.h” is used in the source of
>> the
>> project1 and project2. I ran the “make” with “–j6” option.
>>
>>
>>
>>
>>
>> Project1
>>
>> Project2
>>
>>
>>
>>                     makeFile1
>>
>>
>>
>> in “makeFile1”:
>>
>>
>>
>>        OUTPUT_DIR = path1
>>
>>        INPUT_FILES = \
>>
>>               In_file1\
>>
>>               In_file2
>>
>>
>>
>> include common_makefile
>>
>>
>>
>>
>>
>>                 makeFile2
>>
>>
>>
>> in “makeFile2”:
>>
>>
>>
>>        OUTPUT_DIR = path2
>>
>>        INPUT_FILES = \
>>
>>               In_file3\
>>
>>               In_file4
>>
>>
>>
>> include common_makefile
>>
>>
>>
>>
>>
>>
>> common_makefile
>>
>>
>>
>> in “common_makefile”:
>>
>>
>>
>>   ifndef _COMMON_MAKEFILE_
>>
>>        _COMMON_MAKEFILE_ = 1
>>
>>
>>
>>        OUT_FILE := $(OUTPUT_DIR)\outfile.h
>>
>>        OUT_FILE : INPUT_FILES
>>
>>                COMMAND
>>
>>
>>
>>   endif
>>
>>
>>
>> In Project1:
>>
>>
>>
>> Use “outfile.h”
>>
>> Project2:
>>
>>
>>
>> “Use outfile.h”
>>
>>
>>
>>
>>
>> When I ran a script that calls those two makefiles close to each other,
>> the
>> files are not generated. Though, I see the OUTPUT_DIR is created for
>> project2.
>>
>> If I comment the “  ifndef _COMMON_MAKEFILE_ … endif” block in the
>> “common_makefile”, and ran the script again, then I get the generated
>> “outfile.h” in the OUTPUT_DIR for project2,
>>
>> but the content of it tells me that it’s a file for project1. So, it
>> seems,
>> some race condition is happening when accessing the common_makefile at the
>> same time. Is there a way to run the “common_makefile” sequentially,
>> first,
>> for project1, and then, for project2? Thank you.
>>
>>
>>
>>
>>
>> Tanya.
>> _______________________________________________
>> Help-make mailing list
>> [hidden email]
>> https://lists.gnu.org/mailman/listinfo/help-make
>>
>
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[hidden email]
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