[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
URL:
  <http://savannah.gnu.org/bugs/?51292>

                 Summary: Handling make rules where prerequisites are
determined by functions for specific targets lists
                 Project: make
            Submitted by: elfring
            Submitted on: Thu 22 Jun 2017 03:10:13 PM CEST
                Severity: 3 - Normal
              Item Group: Enhancement
                  Status: None
                 Privacy: Public
             Assigned to: None
             Open/Closed: Open
         Discussion Lock: Any
       Component Version: 4.2.1
        Operating System: Any
           Fixed Release: None
           Triage Status: None

    _______________________________________________________

Details:

Static pattern rules
<https://www.gnu.org/software/make/manual/html_node/Static-Usage.html> can be
used like in the following example.


objects::=foo.o bar.o

$(objects): %.o: %.c
        $(CC) -c $(CFLAGS) $< -o $@



Such a specification seems to indicate that the placeholder “%” can only
be mapped to a stem if the passed targets contain the same suffix (and/or
prefix) which was also specified by the target pattern.
I find that this approach requires then the use of duplicate data. I would
prefer to avoid that because of general software design principles
<https://en.wikipedia.org/wiki/Don%27t_repeat_yourself>.

I would prefer in some use cases to work directly with the targets list in the
way by appending (or prepending) something to a file name (instead of
performing the previous data extraction operation).

I imagine that an other syntax variant could express additional possibilities
for a better handling of desired prerequisites there. I suggest to let
customisable callback functions
<https://en.wikipedia.org/wiki/Callback_(computer_programming)> decide which
data transformations should be finally applied.

How do you think about to add support for such advanced generation of make
rules?




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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Additional Item Attachment, bug #51292 (project make):

File name: makefile                       Size:0 KB
File name: gcomp.scm                      Size:0 KB


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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Follow-up Comment #1, bug #51292 (project make):

Example by Mike Gran:

$(objects):
        $(foreach X,$@,\
        $(guile (gcomp "$(X)")))
        @true


I would like to see a kind of function call for the specification of
prerequisites (instead of the shown function calls in the recipe).

A variant of the shown small Guile source file might be usable for the
proposed usage of a corresponding callback function.

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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Follow-up Comment #2, bug #51292 (project make):

Is this what you mean?

CFLAGS = -g -O2 -Wall

all: demo

define GCOMP2
(define (root->list-of-objects target)
  (list (string-append target "_foo.o")
        (string-append target "_bar.o")))
#f
endef

$(guile $(GCOMP2))

demo: $(guile (root->list-of-objects "demo"))
        $(CC) $(LDFLAGS) -o $@ $^


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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Follow-up Comment #3, bug #51292 (project make):

Another example by Mike Gran:

demo: $(guile (root->list-of-objects "demo"))
        $(CC) $(LDFLAGS) -o $@ $^


You showed an other interesting use case. It seems that only simple input file
dependencies would be constructed.
I guess that the concrete function parameter "demo" can also be replaced by a
corresponding variable reference.

It fits only partly to the proposed software extension which should perform
generation of make rules similar to static pattern rules.


I imagine that it will become a general software development challenge to
achieve consensus for the required parameters of such callback functions (and
the corresponding notation).

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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Update of bug #51292 (project make):

                  Status:                    None => Wont Fix              
             Open/Closed:                    Open => Closed                

    _______________________________________________________

Follow-up Comment #4:

You can easily add the suffix as part of the static pattern rule:


targets ::= foo bar

$(targets:=.o): %.o: %.c
        $(CC) -c $(CFLAGS) $< -o $@
-vebatim-

If you want a "callback"-like setup you can already do it with eval and call:


# Function to generate a new rule.
# Call syntax: $(call new_rule,<target>,<callback_fn_name>)
define new_rule
$1 : $$(call $2,$1)
        $$(CC) -c $$(CFLAGS) $$< -o $$@
endef

# Example use
targets = foo bar biz

foo_prereq = foo1 foo2 foo3
bar_prereq = $(addsuffix .xx,$1)
biz_prereq = $(addprefix $1,.a .b .c)

$(foreach T,$(targets),$(eval $(call new_rule,$T,$T_prereq)))


You can of course also add other callbacks, for the target, recipe, etc.

Personally I'm not convinced this is useful in general... it's certainly a lot
less readable (to me).  But if you had one set of global makefiles that
defined all the templates, etc. then used data-driven variable assignments to
do the rest I suppose it might be useful.

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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Follow-up Comment #5, bug #51292 (project make):

Bleah, typo.  Rewriting:

You can easily add the suffix as part of the static pattern rule:


targets ::= foo bar

$(targets:=.o): %.o: %.c
        $(CC) -c $(CFLAGS) $< -o $@


If you want a "callback"-like setup you can already do it with eval and call:


# Function to generate a new rule.
# Call syntax: $(call new_rule,<target>,<callback_fn_name>)
define new_rule
$1 : $$(call $2,$1)
        $$(CC) -c $$(CFLAGS) $$< -o $$@
endef

# Example use
targets = foo bar biz

foo_prereq = foo1 foo2 foo3
bar_prereq = $(addsuffix .xx,$1)
biz_prereq = $(addprefix $1,.a .b .c)

$(foreach T,$(targets),$(eval $(call new_rule,$T,$T_prereq)))


You can of course also add other callbacks, for the target, recipe, etc.

Personally I'm not convinced this is useful in general... it's certainly a lot
less readable (to me).  But if you had one set of global makefiles that
defined all the templates, etc. then used data-driven variable assignments to
do the rest I suppose it might be useful.

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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Follow-up Comment #6, bug #51292 (project make):

Was your feedback truncated by the tracking interface for this issue?

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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Follow-up Comment #7, bug #51292 (project make):

> If you want a "callback"-like setup you can already do it with eval and
call:

This approach might be an approximation which can work as usual for a while.


> Personally I'm not convinced this is useful in general...

I dared to propose a software extension which can be similar to the
functionality “static pattern rules”.
Under which circumstances can the generic variant move into the standard
functions?


> But if you had one set of global makefiles that defined all the templates,
etc. then used data-driven variable assignments to do the rest I suppose it
might be useful.

Thanks that you can follow in this software design direction.

I imagine that make rule construction can become more dynamic.

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[bug #51292] Handling make rules where prerequisites are determined by functions for specific targets lists

Robert Morell
Follow-up Comment #8, bug #51292 (project make):

> I dared to propose a software extension which can be similar to the
functionality “static pattern rules”. Under which circumstances can the
generic variant move into the standard functions?

I don't see any need to move something like this "into the standard
functions".  If you want to be able to define a rule using a function syntax
instead of a normal recipe syntax you can do this today with something like:


basic_rule = $1 : $2 ; $3

$(eval $(call basic_rule,target,prereq1 prereq2,recipe))



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