[bug #51434] Document that variables are treated differently in prerequisite lists and recipes

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[bug #51434] Document that variables are treated differently in prerequisite lists and recipes

Robert Morell
URL:
  <http://savannah.gnu.org/bugs/?51434>

                 Summary: Document that variables are treated differently in
prerequisite lists and recipes
                 Project: make
            Submitted by: None
            Submitted on: Mon 10 Jul 2017 02:11:04 PM UTC
                Severity: 3 - Normal
              Item Group: Documentation
                  Status: None
                 Privacy: Public
             Assigned to: None
             Open/Closed: Open
         Discussion Lock: Any
       Component Version: None
        Operating System: POSIX-Based
           Fixed Release: None
           Triage Status: None

    _______________________________________________________

Details:

The same variable is expanded at different times depending on whether it is
used in a pre-requisites list or a recipe but this counter-intuitive
difference is not documented anywhere.  It is the same for both "flavors" of
variables.

Consider the following example

VARS=a.c b.c

p: $(VARS)
        echo i am using  $(VARS) to build
        echo $(VARS) > p

VARS=x.c y.c

Here $(VARS) in the prerequisite list is expanded when make reads that line of
the file (to "a.c b.c") but the $(VARS) in the recipe on the next line is
expanded to its value at the end of the makefile (here "x.c y.c")

A demonstration of the effect using the above example follows. In summary it
builds p using x.c and y.c but build is triggered when a.c and b.c are
touched

[x@m1 temp/make.vars]$ make
echo i am using  x.c y.c to build
i am using x.c y.c to build
echo x.c y.c > p
[x@m1 temp/make.vars]$ touch x.c
[x@m1 temp/make.vars]$ make
make: `p' is up to date.
[x@m1 temp/make.vars]$ touch b.c
[x@m1 temp/make.vars]$ make
echo i am using  x.c y.c to build
i am using x.c y.c to build
echo x.c y.c > p
[x@m1 temp/make.vars]$ vi
[x@m1 temp/make.vars]$ make --version
GNU Make 3.82
Built for i386-redhat-linux-gnu
Copyright (C) 2010  Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
[x@m1 temp/make.vars]$






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[bug #51434] Document that variables are treated differently in prerequisite lists and recipes

Robert Morell
Additional Item Attachment, bug #51434 (project make):

File name: makefile                       Size:0 KB


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[bug #51434] Document that variables are treated differently in prerequisite lists and recipes

Robert Morell
Update of bug #51434 (project make):

                  Status:                    None => Not A Bug              
             Open/Closed:                    Open => Closed                

    _______________________________________________________

Follow-up Comment #1:

There is a section of the GNU make manual dedicated to discussing the ways in
which variable expansion differs around make constructs; see:

https://www.gnu.org/software/make/manual/html_node/Reading-Makefiles.html

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Re: [bug #51434] Document that variables are treated differently in prerequisite lists and recipes

Edward Welbourne-3
In reply to this post by Robert Morell
> VARS=a.c b.c
>
> p: $(VARS)
> echo i am using  $(VARS) to build
> echo $(VARS) > p
>
> VARS=x.c y.c
>
> Here $(VARS) in the prerequisite list is expanded when make reads that
> line of the file (to "a.c b.c") but the $(VARS) in the recipe on the
> next line is expanded to its value at the end of the makefile (here
> "x.c y.c")

... which is a good reason for using $^ in the rule (it'll be the full
list of prerequisites, so match what $(VARS) was when the rule was
parsed); another thing worth mentioning in your proposed documentation
revision.

        Eddy.

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