using $eval to include other makefiles

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using $eval to include other makefiles

Hiran Morar
Hello,

I've noticed multiple ways of including a Makefile within another Makefile.
For example, one could directly include the Makefile:

     # Filename top.mk
     ...
     include /path/to/file.mk

One could also use the $eval function to include the Makefile:

     # Filename: top.mk
     ...
     $(eval include /path/to/file.mk)

Both work fine. What's the difference? Is there an optimal or preferred
method?

Thanks!
Hiran
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RE: using $eval to include other makefiles

Rakesh Sharma-6

Let me quote from the GNU make manual on the "eval function". It says:
The argument to the eval function is expanded, then the results of that expansion are parsed as makefile syntax.
Now in this case, of $(eval include /path/to/file.mk)the two arguments to eval are the keyword include & the fullpath of file.mk
Since there are no characters to be expanded here, so in essence it's a constant. Hence the resultsbefore & after the expansion are the same & then make performs the actions indicated by thearguments, which is including the file into the current makefile.
So, FAPP these two syntaxes are identical in this case.
Also, eval is normally employed when the arguments to it contain varying things to be able to showoff it's versatility.
-Rakesh

> Date: Wed, 22 Jul 2015 20:02:00 -0700
> Subject: using $eval to include other makefiles
> From: [hidden email]
> To: [hidden email]
>
> Hello,
>
> I've noticed multiple ways of including a Makefile within another Makefile.
> For example, one could directly include the Makefile:
>
>      # Filename top.mk
>      ...
>      include /path/to/file.mk
>
> One could also use the $eval function to include the Makefile:
>
>      # Filename: top.mk
>      ...
>      $(eval include /path/to/file.mk)
>
> Both work fine. What's the difference? Is there an optimal or preferred
> method?
>
> Thanks!
> Hiran
> _______________________________________________
> Help-make mailing list
> [hidden email]
> https://lists.gnu.org/mailman/listinfo/help-make
     
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RE: using $eval to include other makefiles

Rakesh Sharma-6
Hello Hiran,
[Please retain the Cc:  to the GNU Make.org site so that a proper account of the mail thread remains,but more importantly, so that the real experts of gmake can then chime in.]
I am not sure that the syntax snippet you've shown is make or even gnu-make. Can you do a "make   --version"    on your terminal command line & let me know it's output.
"mk_file" appears to me to be some sort of a shell variable rather than make variable.  So that makes the $(eval ...) to not be a constant string.
BTW, from the looks of the snippet it appears that you are trying to do an includeby first ensuring the existence of the file.mk. Actually, that functionality comeswith the gnu make's "include" command itself, a "-" before prefixing the include, like as,   -include  file.mkor,   sinclude  file.mk    <--- (the `silent' include) for compatibility with other makes, e.g., solaris
Then you won't get to hear from gnu make even if file.mk didn't exist.
Another way to accomplish in gnu make, an include by first ensuring the existence is:
ifneq ($(strip $(wildcard file.mk)),)include file.mkendif
HTH
-Rakesh
Date: Tue, 28 Jul 2015 02:42:21 -0700
Subject: Re: using $eval to include other makefiles
From: [hidden email]
To: [hidden email]

Hi Rakesh,
Thanks for clarifying.
I am conditionally including a Makefile within  my Makefile, via template expansion. I have a function that will return if a specified Makefile exists.

For example:
{%-  set  mk_file = find_makefile('file.mk')  -%}{%-  if mk_file is not none  %}$(eval include {{  mk_file  }})(%  endif  -%)
Please correct me if I'm wrong, but even in this case, syntax would be identical, whether I use $eval function or just include the Makefile directly. Because still, there are no characters to be expanded here, and the two arguments to eval remain the same.
Thanks again!Hiran
On Thu, Jul 23, 2015 at 2:03 AM, Rakesh Sharma <[hidden email]> wrote:




Let me quote from the GNU make manual on the "eval function". It says:
The argument to the eval function is expanded, then the results of that expansion are parsed as makefile syntax.
Now in this case, of $(eval include /path/to/file.mk)the two arguments to eval are the keyword include & the fullpath of file.mk
Since there are no characters to be expanded here, so in essence it's a constant. Hence the resultsbefore & after the expansion are the same & then make performs the actions indicated by thearguments, which is including the file into the current makefile.
So, FAPP these two syntaxes are identical in this case.
Also, eval is normally employed when the arguments to it contain varying things to be able to showoff it's versatility.
-Rakesh

> Date: Wed, 22 Jul 2015 20:02:00 -0700
> Subject: using $eval to include other makefiles
> From: [hidden email]
> To: [hidden email]
>
> Hello,
>
> I've noticed multiple ways of including a Makefile within another Makefile.
> For example, one could directly include the Makefile:
>
>      # Filename top.mk
>      ...
>      include /path/to/file.mk
>
> One could also use the $eval function to include the Makefile:
>
>      # Filename: top.mk
>      ...
>      $(eval include /path/to/file.mk)
>
> Both work fine. What's the difference? Is there an optimal or preferred
> method?
>
> Thanks!
> Hiran
> _______________________________________________
> Help-make mailing list
> [hidden email]
> https://lists.gnu.org/mailman/listinfo/help-make
     

     
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